Unlike conventional packaging technology that processes a single chip at a time, advanced wafer-level packaging technology can process an entire redistribution structure. In other words, multiple chips included in the redistribution structure can be processed together before the chips are separated individually, hence simplifying a back-end process of chip packaging and reducing manufacturing time and cost. That is, the back-end process can be applied to the entire redistribution structure, and then the redistribution structure can be sawn into multiple, individual semiconductor device packages. In view of these benefits, advanced wafer-level packaging technology is becoming a mainstream technology of semiconductor device packages.
During the fabrication of a redistribution structure, multiple devices can be sawn from a wafer and positioned on a carrier. The devices can include multiple chips with circuit functionality and multiple alignment dies. In a subsequent exposure process, a mask alignment tool can position a mask to perform an exposure process for forming a dielectric layer or an electrically conductive layer on the redistribution structure surface, according to the alignment dies included in the redistribution structure. Unfortunately, the devices on the carrier may be misplaced or may be displaced during the fabrication of the redistribution structure, and an alignment bias can result from such misplacement or displacement. In some instances, the alignment bias can be as high as +/−10 μm. As a result, a fabricated pattern, such as a pattern of a dielectric layer or an electrically conductive layer, can be displaced to an undesirable extent, relative to its intended position in the absence of an alignment bias.
Referring to FIG. 1, an alignment bias that can result from the use of alignment dies 100 and 104′ is shown in accordance with a conventional approach. After the alignment dies 100 and 104′ are positioned on a carrier, a rotational bias can occur, yielding a bias angle A between an alignment mark 102 on the alignment die 100 and an alignment mark 106′ on the alignment die 104′. The off-center positioning of the alignment mark 102 on the alignment die 100 and the off-center positioning of the alignment mark 106′ on the alignment die 104′ exacerbates the extent of the bias angle A and its resulting effects on fabricated patterns. In a subsequent exposure process, a mask alignment tool can position a mask according to the alignment mark 102 and the alignment mark 106′, which are already biased. As such, the mask is positioned so as to generate a rotational bias, and the resulting fabricated patterns can be significantly displaced relative to their intended positions.
It is against this background that a need arose to develop the semiconductor device packages, redistribution structures, and manufacturing methods described herein.